The invention relates generally to the field of electronics. More particularly, the invention relates to amplifier biasing.
In amplifier design, a biasing circuit or network is intended to set and maintain the direct current (DC) bias point for the amplifier, allowing an amplifier to operate at an appropriate point in the amplifier""s transfer characteristic. A bias network is intended to provide bias stability when there are variations in input signals, circuit parameters, or circuit conditions. The biasing circuit used for an amplifier will have significant effect on the operation of the amplifier.
However, conventional bias networks do not address all issues in amplifier operation and may not provide a DC bias point that is sufficiently stable and accurate under all circumstances. A conventional bias network may not sufficiently inhibit large signal de-biasing of the amplifier. Further, conventional bias networks may allow significant power gain variations as a function of input power, in which the power gain compresses as the input power is increased.
FIG. 1 is an illustration of a conventional bias network that may be used in a radio frequency (RF) power amplifier. Transistors Q1 125 and Q3 135 make up a simple current mirror reference for an RF power transistor Q2 170. Ib 115 is a current source coupled between the current mirror and voltage source VCC 185. The bias current for Q2 is provided by diode Q4 140 and resistor R2 145, with stability of the bias network being provided by dominant pole capacitor C3 120. For stability, a capacitor across R3 130 is sometimes also needed to provide feed-forward compensation. Resistor R1 150 is intended to provide RF isolation of the bias network and prevent loading of the input 105. The input is alternating current (AC) coupled to the base of transistor Q2 170 via capacitor C2 155.
In FIG. 1, the output collector of Q2 170 is biased with inductor Lc 160, the other end of inductor Lc 160 being coupled to voltage source VCC 185. The output port 110 will typically drive a 50-Ohm matching network. The emitter inductor Lc 175 shown between the emitter of Q2 170 and ground 180 represents the package impedance, the inductance created by typical package ground impedance and/or bond wires. Resistor R3 130 is inserted between the base of Q1 125 and the emitter of Q3 135 to provide base current compensation. The voltage drop across R1 is the base current error voltage Verr=Ib2xc3x97R1, where Ib2 is the base current of Q2 170. To compensate for this error voltage, the drop across R3 should be equal to Verr when the collector current of Q2, Ic2 165, is equal to a given multiple of the collector current of Q1 Ic1 190, Ic2=Mxc3x97Ic1. To provide such current at this point, the resistance of R3 should be equal to the multiple of the resistance of R1, R3=Mxc3x97R1.
The conventional bias network shown in FIG. 1 may provide stabilization of the DC bias point as a function of certain factors such as temperature and process variation, but such network does not operate to prevent de-biasing when large signals are imposed on the input port. This failure is due to non-linear rectification effects that occur as the output transistor Q2 170 transitions from small signal or Class A mode to large signal or Class B mode. The de-biasing effect also causes the power gain to compress (drop in value) at a lower input power level as the bias point sags. A further complication of the de-biasing effect with conventional biasing occurs in circuit design, in which long, time-consuming transient simulations may be needed to determine the final steady state, large signal response. The slow simulation process is the result of the slow settling time of the steady state bias point in operations with the conventional bias network.